1. Field of the Invention
The present invention relates to a memory module, and particularly relates to a load-reduced memory module having an error correction chip mounted thereon.
2. Description of Related Art
A memory module such as a DIMM (Dual Inline Memory Module) is configured to have many memory chips such as a DRAM (Dynamic Random Access Memory) mounted on a module substrate. Such a memory module is mounted on a memory slot provided on a mother board, thereby transferring data between a memory controller and the memory slot. Because the memory capacity required by a system is very large in recent years, securing a necessary memory capacity by one memory module has been difficult. Therefore, plural memory slots are normally provided on the mother board, thereby making it possible to mount plural memory modules in many cases.
However, when plural memory modules are mounted, the load capacitance of a data wiring on the mother board becomes large, and the signal quality is degraded. This is not a serious problem when a data transfer rate between a memory controller and a memory module is relatively low. However, when a data transfer rate between a memory controller and a memory module becomes higher, data cannot be transferred correctly due to degradation of the signal quality. In recent years, a data transfer rate of about 1.6 to 3.2 Gbps is required. Therefore, to achieve such a high-speed transfer, the load capacitance of a data wiring on the mother board needs to be sufficiently reduced.
A so-called a fully-buffered memory module has been known as a memory module in which the load capacitance of a data wiring can be reduced (Japanese Patent Application Laid-open No. 2008-135597). In the fully-buffered memory module, write data supplied from a memory controller is once all received by an exclusive chip called an advanced memory buffer (AMB), and the data is supplied to a predetermined memory chip. A read operation is performed in an opposite manner, that is, read data output from a memory chip is once all supplied to an AMB, and the data is supplied to a memory controller from the AMB. Because the load capacitance of each memory chip is not visible from the memory controller, the load capacitance of a data wiring is reduced substantially.
However, the AMB used for the fully-buffered memory module is a highly functional chip and is relatively expensive. Therefore, the price of the memory module becomes substantially high. Further, according to the fully-buffered memory module, an interface between a memory controller and the AMB is different from a normal interface between a memory controller and a memory chip, and therefore a conventional memory controller cannot be directly used.
Due to the above background, a memory module referred to as “load-reduced memory module” has been proposed in recent years. The load-reduced memory module uses a relatively simple memory buffer having a register function instead of an AMB. Because a memory buffer is a chip only buffers data and a signal such as a command and an address, the memory buffer can be provided at low cost. Further, because the interface between a memory controller and a memory buffer is not different from a normal interface between a memory controller and a memory chip, the conventional memory controller can be directly used.
Meanwhile, a memory module often has mounted thereon an error correction chip that stores an error correction code not only a regular memory chip (a regular chip) to store user data. The error correction chip is accessed simultaneously with the regular chip, thereby reading an error correction code simultaneously with reading of user data, or writing an error correction code simultaneously with writing of user data.
Normally, error correction chips are collectively arranged on a back surface of a memory buffer. However, when error correction chips are collectively arranged on the back surface of the memory buffer, a topology of a wiring connecting a memory buffer and an error correction chip becomes different from that of a wiring connecting a memory buffer and a regular chip. Therefore, it becomes difficult to satisfy the signal quality of user data and that of an error correction code at the same time, and a high data transfer rate cannot be achieved.
In one embodiment, there is provided a memory module that includes: a module substrate having a plurality of external terminals arranged in a first direction; a plurality of memory chips mounted on the module substrate; and a memory buffer that is mounted on the module substrate and buffers a data signal transmitted and received between at least the memory chips and the external terminals, wherein the memory chips include: a plurality of regular chips including at least first to fourth regular chips that store therein user data contained in the data signal; and a plurality of error-correction chips including first to fourth error-correction chips that store therein an error correction code contained in the data signal to correct an error of the user data, the module substrate has first and second mounting areas of different coordinates in the first direction, the second mounting area has third and fourth mounting areas of different coordinates in a second direction different from the first direction, the first and second regular chips are oppositely arranged on a surface and a back surface of the module substrate in the first mounting area, the third and fourth regular chips are oppositely arranged on the surface and the back surface of the module substrate in the first mounting area, the first and second error-correction chips are oppositely arranged on the surface and the back surface of the module substrate in the third mounting area, the third and fourth error-correction chips are oppositely arranged on the surface and the back surface of the module substrate in the third mounting area, the first error-correction chip and the third error-correction chip are adjacently arranged in the first direction, the second error-correction chip and the fourth error-correction chip are adjacently arranged in the first direction, and the memory buffer is arranged in the fourth mounting area.
According to the present invention, a topology of a wiring connecting a memory buffer and an error correction chip can be matched with that of a wiring connecting a memory buffer and a regular chip. Therefore, it becomes possible to satisfy the signal quality of user data and that of an error correction code at the same time. As a result, a high data transfer rate can be achieved.